1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the present invention relates to a semiconductor memory device which operates at a low level power supply voltage.
2. Description of the Related Art
FIG. 13 is an example of a semiconductor memory device. In FIG. 13, a sense amplifier 101 is disposed between a pair of bit signal lines BL and #BL, and an N-channel transistor 102 is inserted between the sense amplifier 101 and a ground. A P-channel transistor 103 is inserted between the sense amplifier 101 and a power supply potential Vcc. In addition, a memory capacitor 105 is connected to the bit signal line BL via a transistor 104, and a word signal line 106 is connected to a gate of the transistor 104.
The sense amplifier 101 includes P-channel transistors 111 and 112 and N-channel transistors 113 and 114. The P-channel transistor 111 and the N-channel transistor 113, which are on the left side of the sense amplifier 101, are serially connected. The bit signal line BL is connected to a point between the transistors 111 and 113, and the bit signal line #BL is connected to the gates of the transistors 111 and 113. Similarly, the P-channel transistor 112 and the N-channel transistor 114, which are on the right side of the sense amplifier 101, are serially connected. The bit signal line #BL is connected to a point between these transistors 112 and 114, and the bit signal line BL is connected to the gates of the transistors 112 and 114.
In such a structure, when the transistor 104 is turned ON via the word signal line 106, a signal charge of the memory capacitor 105 is transferred to the bit signal line BL, thereby generating a potential difference between the bit signal lines BL and #BL. Although this potential difference is very small, when the N-channel transistor 102 and the P-channel transistor 103 are turned ON at an appropriate timing described below, the potential difference between the bit signal lines BL and #BL is amplified by the sense amplifier 101. As a result, one of the bit signal lines BL and #BL which has a lower potential decreases toward a ground potential, and the other one of the bit signal lines BL and #BL which has a higher potential increases toward the power supply potential Vcc. This enables the signal charge of the memory capacitor 105 to be readily read out or rewritten.
Since a semiconductor memory device includes a large number of the memory capacitors 105, the bit signal lines BL and #BL, and the sense amplifiers 101, the large number of sense amplifiers 101 are operated at the same time. As a result, a large momentary current is generated within the memory device. At this time, a voltage drop due to a line resistance which supplies the power supply potential Vcc to each of the sense amplifiers 101 becomes large. This causes a voltage drop of the sense amplifier 101 to be small (i.e., a potential difference between a source and a drain of each of the transistors in the sense amplifier 101 becomes small), thereby resulting in a slow amplification by the sense amplifier 101.
In order to overcome such amplification delay by the sense amplifier 101, it is necessary to adjust the timing for turning ON the N-channel transistor 102 and the P-channel transistor 103.
As one example of a method for adjusting the timing is described below. As shown in a timing chart of FIG. 14, a signal SN1 is switched to a high level at a point t1, thereby turning ON the N-channel transistor 102, and one of the bit signal lines BL or #BL which has a lower potential decreases toward the ground potential through the N-channel transistor 102 and one of the N-channel transistors 113 or 114 in the sense amplifier 101. At a point t2, a signal SP1 is switched to a low level, thereby turning ON the P-channel transistor 103, and the other one of the bit signal lines BL or #BL which has a higher potential increases toward the power supply potential Vcc through the P-channel transistor 103 and one of the P-channel transistors 111 or 112 in the sense amplifier 101.
In the above-described case, since the driving capabilities of the N-channel transistors 113 and 114 are high, the bit signal line which has a lower potential can be quickly decreased toward the ground potential. On the contrary, the driving capabilities of the P-channel transistors 111 and 112 are low, i.e., their threshold voltages are high, and their capabilities to supply current are low. As a result, it takes additional time to make the bit signal line which has a higher potential increase toward the power supply potential Vcc. The additional time period is equal to the time lag of the point t2 with respect to the point t1 (t2-t1) plus the time required for the bit signal line to reach the power supply potential Vcc, thereby resulting in a slow operating speed of the sense amplifier 101.
Alternatively, there is another method for adjusting the timing which is shown in a timing chart of FIG. 15. At a point t1, a signal SP1 is switched to a low level, thereby turning ON the P-channel transistor 103, and one of the bit signal lines increases toward the power supply potential Vcc. At a point t2, a signal SN1 is switched to a high level, thereby turning ON the N-channel transistor 102, and the other one of the bit signal lines quickly decreases toward the ground potential.
In such a case, since the P-channel transistor 103 is turned ON first and thus the P-channel transistors 111 and 112 which have low driving capabilities are given priority, the operating speed of the sense amplifier 101 is improved as compared to the method shown in FIG. 14.
Also, there is another method for adjusting the timing as shown in a timing chart of FIG. 16. At a point t1, a signal SP1 is switched to a low level, thereby turning ON the P-channel transistor 103, and one of the bit signal lines increases toward the power supply potential Vcc. At the same time, a signal SN1 is switched to a high level, thereby turning ON the N-channel transistor 102, and the other one of the bit signal lines decreases toward the ground potential.
In this case, as compared to the methods shown in FIGS. 14 and 15, a period between the point t1 and t2 can be omitted. However, since the driving by the P-channel transistors 111 and 112 and the driving by the N-channel transistors 113 and 114 in the sense amplifier 101 are started at the same time, a feedthrough current flowing through the sense amplifier 101 is generated. As a result, the ground potential is apparently increased from the standpoint of the sense amplifier. Accordingly, the potential of the bit signal line does not drop rapidly, and thus the improvement in the operating speed of the sense amplifier 101 is small.
As described above, the delay in the amplification by the sense amplifier 101 can be adjusted in accordance with the setting of the timing for turning ON the N-channel transistor 102 and the P-channel transistor 103.
Also, there is another method which incorporates additional transistors as shown in FIG. 17. According to this method, a first P-channel transistor 121 having a small current supplying capability and a second P-channel transistor 122 having a large current supplying capability are inserted in parallel between the sense amplifier 101 and the power supply potential Vcc. As shown in a timing chart of FIG. 18, at a point t1, signals SN1 and SP1 are switched to a high level and a low level, respectively, thereby turning ON an N-channel transistor 102 and the first P-channel transistor 121. One of the bit signal lines decreases toward a ground potential whereas the potential of the other one of the bit signal lines is prevented from dropping. At a point t2, a signal SP2 is switched to be a low level, thereby turning ON the second P-channel transistor 122, and the other one of the bit signal lines quickly increases toward the power supply potential Vcc.
In this case, as compared to the method shown in FIG. 16, the feedthrough current flowing through the sense amplifier 101 is reduced, thereby improving the operating speed to the same level as in the method shown in FIG. 15.
Recently, however, there is a tend to reduce the power supply potential in order to realize a reduction in the power consumption of a semiconductor memory device. For example, the power supply potential is reduced to from level of about 5V to about 3.3V.
When the power supply potential is reduced as described above, the amount of current supplied by the transistor 103 or 122 inserted between the sense amplifier 101 and the power supply potential Vcc is reduced. As a result, the amplification by the sense amplifier 101 for making the bit signal line increase toward the power supply potential Vcc is further delayed. Thus, even with any one of the methods shown in FIGS. 14, 15, 16, and 18, the amplification speed of the sense amplifier 101 cannot be sufficiently increased.
In consideration of this result, there is another method which incorporates additional transistors as shown in FIG. 19. According to this method, two power supply potentials, the power supply potential Vcc and a high level power supply potential Vpp which is obtained by boosting the voltage of the power supply potential Vcc, are provided. In addition, an N-channel transistor 123 is inserted between the low level power supply potential Vcc and the sense amplifier 101, and a P-channel transistor 124 is inserted between the high level power supply potential Vpp and the sense amplifier 101 (see Japanese Laid-open Publication No. 4-281291).
In this case, as shown in a timing chart of FIG. 20, both signals SN1 and SN2 are switched to a high level at a point t1. The N-channel transistor 102 and the N-channel transistor 123 on the side of the low level power supply potential Vcc are turned ON. One of bit signal lines decreases toward a ground potential whereas the potential of the other one of the bit signal lines is prevented from dropping. At a point t2 where a potential difference between the bit signal lines has developed to a certain degree, a signal SP2 is switched to a low level, thereby turning ON the P-channel transistor 124, and the other one of the bit signal lines increases toward the high level power supply potential Vpp.
In this case, since the bit signal line with the high potential attempts to reach the high level power supply potential Vpp, the current supplied by the P-channel transistor 124 does not decline at least until the potential of the appropriate bit signal line exceeds the low level power supply potential Vcc. As a result, the potential of this bit signal line rapidly reaches the low level power supply potential Vcc (Vcc is the potential needed for the signal charge of the memory capacitor 105 to be read out and rewritten). However, since the current supplying capability of the N-channel transistor 102 is large and the feedthrough current flowing through the sense amplifier 101 is not negligible, the ground potential is apparently raised from the standpoint of the sense amplifier and a drop in the potential of the bit signal line is delayed.
Similarly, there is a method which incorporates additional transistors and other circuit components as shown in FIG. 21. According to this method, the low level power supply potential Vcc and the high level power supply potential Vpp are provided as power supply potentials. A first P-channel transistor 125 is inserted between the low level power supply potential Vcc and the sense amplifier 101, and a second P-channel transistor 126 is inserted between the high level power supply potential Vpp and the sense amplifier 101. A diode 127 for preventing reverse current conduction is inserted between the first P-channel transistor 125 and the second P-channel transistor 126.
As shown in a timing chart of FIG. 22, at a point t1, the N-channel transistor 102 and the first P-channel transistor 125 on the side of the low level power supply potential Vcc are turned ON. One of the bit signal lines decreases toward a ground potential whereas the potential of the other one of the bit signal lines is prevented from dropping. At a point t2, the second P-channel transistor 126 is turned ON, and the other one of the bit signal lines rapidly increases toward the high level power supply potential Vpp.
With either of the methods shown in FIGS. 20 and 22, however, an improvement in the operating speed of the sense amplifier 101 is still insufficient. Therefore, there is a great need for further increasing the operating speed.